Silicon Labs /SiM3_NRND /SIM3U166_B /SSG_0 /CONFIG

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Interpret as CONFIG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0COUNT0 (NORMAL)SSEL 0 (DISABLED)PHGFREN 0 (DISABLED)PUGFREN

PHGFREN=DISABLED, PUGFREN=DISABLED, SSEL=NORMAL

Description

Module Configuration

Fields

COUNT

Pulse Generator Counter.

SSEL

Speed Select.

0 (NORMAL): The SSG module runs at normal speed, where each pulse and phase cycle consists of 16 ADC clocks.

1 (DOUBLE): The SSG module runs at double speed, where each pulse and phase cycle consists of 8 ADC clocks.

PHGFREN

Phase Generator Free-Run Enable.

0 (DISABLED): The Phase Generator runs only when pulse generation occurs.

1 (ENABLED): The Phase Generator runs when an ADC is enabled, regardless of the Pulse Generator settings.

PUGFREN

Pulse Generator Free-Run Enable.

0 (DISABLED): The COUNT field determines the number of pulses generated by the Pulse Generator.

1 (ENABLED): The Pulse Generator always generates pulses regardless of COUNT unless all outputs are disabled (EX0EN, EX1EN, EX2EN, and EX3EN are all 0).

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